发明名称 MANAGING INSTRUCTION ORDER IN A PROCESSOR PIPELINE
摘要 Executing instructions in a processor includes classifying, in at least one stage of a pipeline of the processor, operations to be performed by instructions. The classifying includes: classifying a first set of operations as operations for which out-of-order execution is allowed, and classifying a second set of operations as operations for which out-of-order execution with respect to one or more specified operations is not allowed, the second set of operations including at least store operations. Results of instructions executed out-of-order are selected to commit the selected results in-order. The selecting includes, for a first result of a first instruction and a second result of a second instruction executed before and out-of-order relative to the first instruction: determining which stage of the pipeline stores the second result, and committing the first result directly from the determined stage over a forwarding path, before committing the second result.
申请公布号 US2016011876(A1) 申请公布日期 2016.01.14
申请号 US201414328951 申请日期 2014.07.11
申请人 Cavium, Inc. 发明人 Mukherjee Shubhendu Sekhar;Kessler Richard Eugene;Carlson David Albert
分类号 G06F9/38;G06F9/30 主分类号 G06F9/38
代理机构 代理人
主权项 1. A method for executing instructions in a processor, the method comprising: classifying, in at least one stage of a pipeline of the processor, operations to be performed by instructions, the classifying including: classifying a first set of operations as operations for which out-of-order execution is allowed, andclassifying a second set of operations as operations for which out-of-order execution with respect to one or more specified operations is not allowed, the second set of operations including at least store operations; and selecting results of instructions executed out-of-order to commit the selected results in-order, the selecting including, for a first result of a first instruction and a second result of a second instruction executed before and out-of-order relative to the first instruction: determining which stage of the pipeline stores the second result, andcommitting the first result directly from the determined stage over a forwarding path, before committing the second result.
地址 San Jose CA US