CDR CIRCUIT AND SEMICONDUCTOR DEVICE

摘要

A clock data recovery (CDR) circuit is provided with a circuit that updates a locked oscillation frequency, with a small loop gain, after phase lock based on a phase-locked loop circuit for a frequency-locked frequency is completed by a frequency-locked loop circuit or during a phase lock operation. Since the locked oscillation frequency is updated with a small loop gain, it is possible to correct a fluctuation in a frequency of an oscillation circuit in the frequency-locked loop circuit without oscillating a phase-locked loop undesirably even during a phase lock operation.

主权项

1. A clock data recovery (CDR) circuit comprising:
a frequency-locked loop circuit that synchronizes a frequency of an oscillation clock signal of an oscillation circuit with a frequency of input data; a phase-locked loop circuit that inputs the oscillation clock signal and outputs a phase-locked clock signal which is synchronized with a phase of the input data; and a drift correction circuit that calculates a correction value on the basis of a phase difference between the input data and the phase-locked clock signal during a phase lock operation or after phase lock completion based on the phase-locked loop circuit after frequency lock based on the frequency-locked loop circuit, and is able to correct an oscillation frequency of the oscillation circuit using the correction value, with a loop gain smaller than that of the frequency-locked loop circuit.