发明名称 |
Fully Capacitive Coupled Input Choppers |
摘要 |
A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having first through fourth chopper transistors, each having a source, a drain and a gate, the input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed. |
申请公布号 |
US2016013787(A1) |
申请公布日期 |
2016.01.14 |
申请号 |
US201514860423 |
申请日期 |
2015.09.21 |
申请人 |
Maxim Integrated Products, Inc. |
发明人 |
Huijsing Johan Hendrik;Fan Qinwen;Makinwa Kofi Afolabi Anthony |
分类号 |
H03K17/081 |
主分类号 |
H03K17/081 |
代理机构 |
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代理人 |
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主权项 |
1. A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage, comprising:
providing an input chopper having first through fourth chopper transistors, each having a source, a drain and a gate, the input chopper having Vinp and Vinn as a differential input; providing an output chopper; capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper; capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being capacitively coupled to the gates of the first and second transistors and the second phase being capacitively coupled to the gates of the third and fourth transistors; and, providing protection of the gates of the first through fourth transistors from excessive voltages. |
地址 |
San Jose CA US |