| 主权项 |
1. A digital interpolator, comprising an input to receive an input signal at a first clock frequency and comprising an output to provide an interpolated signal at a second clock frequency larger than the first clock frequency, the interpolator comprising:
a differentiator connected to the input, an interpolator stage connected to a differentiator output, and an integrator connected to the output and connected to an output of the interpolator stage, wherein the interpolator stage comprises a storage, an adder, a divider and a subtractor wherein an output of the adder is connected to a divider's input, wherein a divider's output is connected to a storage input and wherein a storage output is connected to an input of the adder, wherein a first input of the substractor is connected to the differentiator output and a second input of the subtractor is connected to the divider's output, and wherein a further input of the adder is connected to the differentiator output. |
