| 发明名称 |
STRUCTURE AND METHOD FOR PROTECTING STRESS-SENSITIVE INTEGRATED CIRCUIT |
| 摘要 |
Methods and apparatuses, wherein the method includes reducing stacking stress. The method couples a first die to a compliant layer. The method couples a second die to the compliant layer, wherein the compliant layer at least partially covers a portion of an interface between the first die and the second die, and wherein the compliant layer is formed in a trench in the second die. |
| 申请公布号 |
US2016013136(A1) |
申请公布日期 |
2016.01.14 |
| 申请号 |
US201414329883 |
申请日期 |
2014.07.11 |
| 申请人 |
QUALCOMM Incorporated |
发明人 |
RAMACHANDRAN Vidhya;BAO Zhongping |
| 分类号 |
H01L23/00;H01L25/00;H01L23/31;H01L25/065 |
主分类号 |
H01L23/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a first die; a second die; and a compliant layer coupled to the first die and the second die, wherein the compliant layer at least partially covers a portion of an interface between the first die and the second die, and wherein the compliant layer is formed in a trench in the second die. |
| 地址 |
San Diego CA US |
