| 发明名称 |
SEMICONDUCTOR MEMORY DEVICE INCLUDING THREE-DIMENSIONAL ARRAY STRUCTURE |
| 摘要 |
A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. A number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors may be greater than the source selection transistors. |
| 申请公布号 |
US2016012893(A1) |
申请公布日期 |
2016.01.14 |
| 申请号 |
US201414570535 |
申请日期 |
2014.12.15 |
| 申请人 |
SK hynix Inc. |
发明人 |
AHN Jung Ryul;LEE Yun Kyoung |
| 分类号 |
G11C16/04 |
主分类号 |
G11C16/04 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor memory device including normal memory cells stacked over a substrate, the semiconductor memory device comprising:
source selection transistors coupled to a common source line; source side dummy memory cells coupled between the source selection transistors and the normal memory cells; drain selection transistors coupled to a bit line; and drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells, wherein a number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and wherein a number of the drain selection transistors is greater than a number of the source selection transistors. |
| 地址 |
Icheon-si KR |
