发明名称 |
Memory control circuit, memory control method, and integrated circuit |
摘要 |
<p>Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.</p> |
申请公布号 |
EP2479676(B1) |
申请公布日期 |
2016.01.13 |
申请号 |
EP20120002246 |
申请日期 |
2007.10.15 |
申请人 |
CANON KABUSHIKI KAISHA |
发明人 |
MURAYAMA, KOHEI;SUZUKI, TAKESHI |
分类号 |
G11C5/04;G06F13/16;G11C5/06;G11C7/10;G11C29/02;G11C29/50 |
主分类号 |
G11C5/04 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|