| 摘要 |
A digital filter with a pipeline structure comprises a plurality of processing structures (10, 12) timed by respective clock signals (CLK10, CLK12). Each structure in turn comprises a number of processing modules (A10, B10, C10, D10; A12, B12, C12, D12) for processing input samples (A1, B1, C1, D1). A phase generator (16; 160 to 168) is provided for aligning the aforesaid processing modules (A10, B10, C10, D10; A12, B12, C12, D12) with the input samples (A1, B1, C1, D1) so that each input sample is processed by respective processing modules (A10, A12; B10, B12; C10, C12; D10, D12) of the processing structures (10, 12). An up-sampling buffer (144) and a down-sampling buffer (142), which can be activated when the processing structures (10, 12) operate at different clock frequencies, so that the digital filter comprises at least one first clock domain (CLK10) and at least one second clock domain (CLK12), convert the signal samples between the first clock domain (CLK10) and the second clock domain (CLK12). |
