COMPLEXITY REDUCTION METHOD FOR PARALLEL OPERATIONS OF ERROR CORRECTION DECODER IN WIRELESS COMMUNICATIONS AND APPARATUS THEREOF

摘要

The present invention relates to an apparatus and a method of reducing complexity of parallel operations of an error correction decoder in a wireless communication system. The apparatus includes a bit node module for grouping bit nodes and performing a bit operation according to a parity check matrix rule based on a DVB-S2 standard; a first local memory for storing an output value of the bit node module and providing the output value to a check node module; the check node module for grouping check nodes and performing a check operation using the output value provided from the first local memory according to the parity check matrix rule based on the DVB-S2 standard; a second local memory for storing an output value of the check node module and providing the output value to the bit node module; a memory controller for notifying an address of a memory for storing the output values of the bit node module and the check node module and notifying an address of a memory for storing values to be provided as an input of the bit node module and the check node module; a channel LLR memory for storing channel log likelihood ratio LLR values and inputting a channel LLR value to be used for a bit node operation to the bit node module; and a main controller for performing an iterative decoding operation by controlling selectively the memory controller, the channel LLR memory, the bit node module, the first local memory, the second local memory and the check node module.