发明名称 |
INTEGRATED CIRCUIT FLOORPLAN FOR COMPACT CLOCK DISTRIBUTION |
摘要 |
<p>An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.</p> |
申请公布号 |
EP2965236(A2) |
申请公布日期 |
2016.01.13 |
申请号 |
EP20140711066 |
申请日期 |
2014.02.26 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
SRINIVAS, VAISHNAV;KIM, ROBERT WON CHOL;CLOVIS, PHILIP MICHAEL;WEST, DAVID IAN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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