| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To acquire trace data while reducing an activity ratio of a shared bus. <P>SOLUTION: Processor elements 100 and 200 are interconnected by a shared bus 1. A CPU 201 executes a system call which is an instruction to change a state of a task 109, and transmits a memory access instruction to a task management block 112 via the shared bus 1 by executing the system call 210. The memory access instruction includes an identifier of the CPU 201. A CPU 101 executes processing concerning the task 109 according to the memory access instruction. A trace control unit 106 detects the memory access instruction to the task management block 112, and writes task processing information with the identifier of the CPU 201 in a trace area 107 according to the detected memory access instruction. <P>COPYRIGHT: (C)2013,JPO&INPIT</p> |
