| 摘要 |
<p>There is described a cyclic pipelined Analog-to-Digital Converter having an input (41) adapted to receive an analog voltage (V IN ) to be converted, and an output (42) adapted to deliver a n-bit digital value (N OUT ). The converter also comprises a core stage (40) comprising an Analog-to-Digital Conversion stage (50) to provide at least one bit value of the n-bit digital value at each one of a plurality of successive conversion steps performed in loop by the core stage (40). The core stage (40) further comprises a differential inputs-differential outputs amplifier (59). In order to cancel the offset of the stage (55, 58), the coupling of the amplifier inputs is inversed, i.e. the inputs are switched around, namely swapped, just after the first conversion step has been carried out. Simultaneously the differential outputs of the amplifier are similarly swapped.</p> |
