Flash memory integrated circuit with compression/decompression CODEC

摘要

Provided is a flash memory integrated circuit with a compression codec. The flash memory integrated circuit may simultaneously include a memory block and a compression codec circuit. The compression codec circuit may compress input data. A controller circuit may store the compressed input data in at least one page that is included in the memory block. Through this, it is possible to enhance a usage efficiency of a flash memory.

主权项

1. A flash memory integrated circuit with a compression codec, comprising:
at least one memory block including a plurality of pages; a type decision circuit configured to determine whether input data is compressed by comparing a type of the input data with a predetermined compressing type and to provide a logic value corresponding to the determination; a compression codec circuit configured to compress the input data according to the provided logic value when the input data is uncompressed and not to compress the input data according to the provided logic value when the input data is compressed and to generate identification information indicating that the input data is the compressed input data; and a controller circuit configured to generate a control signal in order to sequentially write the input data when the controller circuit is configured to receive originally compressed input data from the compression codec circuit and a control signal in order to sequentially write the compressed input data and the identification information when the controller circuit is configured to receive the compressed input data and the identification information from the compression codec circuit in at least one page among the plurality of pages, wherein the controller circuit is configured to generate the control signal to control voltages to be applied to a word line or a bit line that is connected to the at least one page.