| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of terminals.SOLUTION: A low speed optical signal processing part 10 includes: an FPGA(Field Programmable Gate Array) 12 for control; an optical module 13a; and a signal amplification device 14a. The FPGA 12 for control outputs a data signal which is common to the optical module 13a and the signal amplification device 14a and a clock signal capable of individually controlling the optical module 13a and the signal amplification device 14a to each of the optical module 13a and the signal amplification device 14a. The FPGA 12 for control controls the optical module 13a and the signal amplification device 14a. |
