Semiconductor device having hierarchically structured bit lines

摘要

Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.

主权项

1. A device comprising:
a first memory mat including: a plurality of first memory cells; a defective memory cell; a first global bit line; a plurality of first local bit lines coupled in common to the first global bit line, each of the first local bit lines coupled to associated ones of the first memory cells, one of the first local bit lines being further coupled to the defective memory cell; and a plurality of first transistors each coupled between an associated one of the first local bit lines and the first global bit line; a second memory mat including: a plurality of second memory cells; a redundant memory cell; a second global bit line; a plurality of second local bit lines coupled in common to the second global bit line, each of the second local bit lines coupled to associated ones of the second memory cells, one of the second local bit lines being further coupled to the redundant memory cell; and a plurality of second transistors each coupled between an associated one of the second local bit lines and the second global bit line, wherein one of the second transistors is coupled between the one of the second local bit lines and the second global bit line; a plurality of terminals receiving access address information; and a control circuit including a storing unit that is configured to store defective address information that designate the defective memory cell of the first memory mat and accessing unit that is configured to access to the redundant memory cell of the second memory mat when the access address information coincides with the defective address information, wherein the accessing unit of the control circuit is configured to render the one of the second transistors conductive when the access address information coincides with the defective address information.