Drift detection in timing signal forwarded from memory controller to memory device

摘要

A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

主权项

1. A memory controller comprising:
a timing signal generation circuit to generate, for transmission to a memory device:
a first timing signal having a first frequency, the first timing signal to be used, by the memory device, for a data transfer operation; anda second timing signal having a second frequency, the second frequency being lower than the first frequency; a circuit to receive from the memory device information indicative of phase delay occurring on the second timing signal associated with timing drift in the memory device, the information including a plurality of digital values, each digital value indicative of phase delay occurring on the second timing signal caused by one of a plurality of delay circuits representing drift characteristics of different portions of distribution of the first timing signal in the memory device; and a phase adjusting circuit to adjust a phase of the first timing signal based on the received information indicative of phase delay occurring on the second timing signal.