Stacked integrated circuit with redundancy in die-to-die interconnects

摘要

An integrated circuit (IC) is provided where the IC includes a first die, a second die stacked above the first die, and a plurality of die-to-die interconnects coupling the first die to the second die, where the plurality of die-to-die interconnects includes at least one redundancy die-to-die interconnect. In one implementation, the plurality of die-to-die interconnects includes a plurality of pre-designated die-to-die interconnects, where if a pre-designated die-to-die interconnect of the plurality of pre-designated die-to-die interconnects is defective, then signals intended for transmission via the pre-designated die-to-die interconnect are instead transmitted via the at least one redundancy die-to-die interconnect.

主权项

1. An integrated circuit (IC) comprising:
a first die including a bottom-die redundancy control circuit; a second die coupled to the first die, the second die including a top-die redundancy control circuit; and a plurality of die-to-die interconnects coupling the bottom-die redundancy control circuit to the top-die redundancy control circuit, wherein the plurality of die-to-die interconnects comprises a plurality of pre-designated die-to-die interconnects and at least one redundancy die-to-die interconnect, wherein the bottom-die redundancy control circuit comprises:
a plurality of pre-designated signal paths; anda redundancy signal path, wherein the redundancy signal path includes a selector coupled to the plurality of pre-designated signal paths,wherein the selector receives signals received by the plurality of pre-designated signal paths and an additional signal, wherein the additional signal is not a select signal for the selector, further wherein the selector selects a signal from its received signals and outputs the signal to a redundancy die-to-die interconnect of the at least one redundancy die-to-die interconnect, further wherein the top-die redundancy control circuit comprises:
a plurality of selectors; anda plurality of decoding logic circuits coupled to the plurality of selectors, wherein each decoding logic circuit of the plurality of decoding logic circuits is coupled to a corresponding selector of the plurality of selectors,wherein each selector of the plurality of selectors receives a signal from a corresponding pre-designated die-to-die interconnect and a signal from a redundancy die-to-die interconnect of the at least one redundancy die-to-die interconnect, further wherein each selector of the plurality of selectors receives a select signal from a corresponding decoding logic circuit of the plurality of decoding logic circuits.