发明名称 Clock data recovery circuit module and method for generating data recovery clock
摘要 A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.
申请公布号 US9237005(B2) 申请公布日期 2016.01.12
申请号 US201514641454 申请日期 2015.03.09
申请人 PHISON ELECTRONICS CORP. 发明人 Chen Chih-Ming;Chen An-Chung
分类号 H04L7/04;H04L7/033;H03L7/085;H04L7/00 主分类号 H04L7/04
代理机构 Jianq Chyun IP Office 代理人 Jianq Chyun IP Office
主权项 1. A crystal-less clock data recovery circuit module, comprising: a clock data recovery circuit, configured to output a data recovery stream and a data recovery clock; a frequency comparison circuit, coupled to the clock data recovery circuit, wherein the frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and a clock signal to adjust a frequency of the clock signal based on a comparison result; and a signal detection circuit, coupled to the frequency comparison circuit and configured to receive and detect a first signal, wherein the signal detection circuit determines whether to enable the frequency comparison circuit according to a detection result, wherein the clock data recovery circuit comprises: a frequency generation circuit, coupled to the frequency comparison circuit and configured to generate the clock signal and output a control signal according to the comparison result; and a clock generation circuit, coupled to the frequency generation circuit and configured to generate the data recovery clock with reference to the clock signal, wherein the frequency generation circuit comprises: a reference clock generation circuit, configured to generate and output a reference clock; and a phase-locked loop circuit, coupled to the frequency comparison circuit, wherein the phase-locked loop circuit is controlled by the control signal and configured to generate the clock signal according to the control signal and the reference clock.
地址 Miaoli TW