Graphene transistor with a sublithographic channel width

摘要

Silicon-carbon alloy structures can be formed as inverted U-shaped structures around semiconductor fins by a selective epitaxy process. A planarization dielectric layer is formed to fill gaps among the silicon-carbon alloy structures. After planarization, remaining vertical portions of the silicon-carbon alloy structures constitute silicon-carbon alloy fins, which can have sublithographic widths. The semiconductor fins may be replaced with replacement dielectric material fins. In one embodiment, employing a patterned mask layer, sidewalls of the silicon-carbon alloy fins can be removed around end portions of each silicon-carbon alloy fin. An anneal is performed to covert surface portions of the silicon-carbon alloy fins into graphene layers. In one embodiment, each graphene layer can include only a horizontal portion in a channel region, and include a horizontal portion and sidewall portions in source and drain regions. If a patterned mask layer is not employed, each graphene layer can include only a horizontal portion.

主权项

1. A method of forming a structure comprising:
forming a silicon-carbon alloy fin located on an insulator layer; forming a graphene layer located on a top surface of said silicon-carbon alloy fin; forming a planarization dielectric material layer contacting said silicon-carbon alloy fin, wherein a horizontal interface between said graphene layer and said silicon-carbon alloy fin is recessed relative to a top surface of said planarization dielectric material layer; and forming a gate structure comprising a stack of a gate dielectric and a gate electrode and straddling said silicon-carbon alloy fin and contacting said to surface of said planarization dielectric material layer.