Integrated circuits and methods for dynamic frequency scaling

摘要

In an integrated circuit, a first delay locked loop circuit is configured to adjust a phase of a first clock signal input to a first clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted first clock signal. A second delay locked loop circuit is configured to adjust a phase of a second clock signal input to a second clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted second clock signal. A path selection circuit is configured to select, in response to a select signal, one of a first signal path through the first delay locked loop circuit and a second signal path through the second delay locked loop circuit as a signal path for at least one of transmitting and receiving the information.

主权项

1. An integrated circuit comprising:
a first delay locked loop circuit configured to adjust a phase of a first clock signal input to a first clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted first clock signal; a second delay locked loop circuit configured to adjust a phase of a second clock signal input to a second clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted second clock signal; and a path selection circuit configured to select, in response to a select signal, one of a first signal path through the first delay locked loop circuit and a second signal path through the second delay locked loop circuit as a signal path for at least one of transmitting and receiving the information; wherein
the select signal is generated during a period in which information is not transmitted between a memory controller and a memory device,the second delay locked loop circuit is in a standby state,the first clock signal is a clock signal currently in use by a memory system, andthe second clock signal is a clock signal to be used by the memory system after the first clock signal.