| 主权项 |
1. A method of processing a circuit design, comprising:
on a programmed processor, performing operations including:
inputting a placed circuit design that has been placed on programmable resources of a programmable integrated circuit (IC);wherein the programmable resources include pluralities of sequential elements, clock buffers, and programmable logic, and the plurality of clock buffers includes a plurality of different types of clock buffers;wherein ones of the plurality of clock buffers that are assigned to the placed circuit design are used clock buffers, and ones of the plurality of clock buffers that are not assigned to the placed circuit design are unused clock buffers;determining a critical path from a first sequential element to a second sequential element, the first and second sequential elements being ones of the plurality of sequential elements assigned to the placed circuit design;determining a first clock buffer of the used clock buffers that provides a clock signal to the first and second sequential elements;selecting one of the unused clock buffers of the same type as the first clock buffer and based on proximity to the first sequential element; andmodifying the placed circuit design to include the one unused clock buffer as a second clock buffer coupled to receive a clock signal in parallel with the first clock buffer and to provide the clock signal to the first sequential element;determining after the modifying, whether or not timing of the clock signal at the first and second sequential elements satisfies a timing constraint;selecting, in response to the timing not satisfying the timing constraint, another unused clock buffer of the unused clock buffers as a third clock buffer, the third clock buffer being of a different type from the first clock buffer; andreplacing the second clock buffer with the third clock buffer in the placed circuit design. |
