Bias to detect and prevent short circuits in three-dimensional memory device

摘要

In a three-dimensional stacked non-volatile memory device, a short circuit in a select gate layer is detected and prevented. A short circuit may occur when charges which are accumulated in select gate lines due to plasma etching, discharge through a remaining portion of the select gate layer in a short circuit path when the select gate lines are driven. To detect a short circuit, during a testing phase, an increasing bias is applied is applied to the remaining portion while a current is measured. An increase in the current above a threshold indicates that the bias has exceed a breakdown voltage of a short circuit path. A value of the bias at this time is recorded as an optimal bias. During subsequent operations involving select gate transistors or memory cells, such as programming, erasing or reading, the optimal bias is applied when the select gate lines are driven to prevent a current flow through the short circuit.

主权项

1. A method for controlling a memory device, comprising:
applying a voltage to a remaining portion of a select gate layer in a stacked three-dimensional memory structure, the stacked three-dimensional memory structure comprising alternating conductive layers and dielectric layers, the select gate layer is one of the conductive layers and comprises parallel select gate lines, the remaining portion of the select gate layer extends transversely to the parallel select gate lines and is separated from the parallel select gate lines by an end trench at one end the of parallel select gate lines, the parallel select gate lines are separated from one another by side trenches, the end trench is connected to the side trenches, an oxide is provided in the end trench and an oxide is provided in the side trenches; detecting a short circuit path in the oxide in the end trench during the applying the voltage; determining a voltage level for counteracting the short circuit path; and biasing the remaining portion of the select gate layer during an operation in the stacked three-dimensional memory structure using the voltage level for counteracting the short circuit path.