发明名称 Liquid crystal display device and manufacturing method thereof
摘要 Provided is a liquid crystal display device, including: a first substrate and a second substrate. On the second substrate, a plurality of gate signal lines, a plurality of data signal lines, a plurality of pixel electrodes provided correspondingly to a plurality of pixels, and a common electrode provided so as to be opposed to the pixel electrodes are formed. An interline pitch of the gate signal lines is smaller than an interline pitch of the data signal lines. In each of the pixels, the pixel electrode overlaps, in plan view, gate signal lines adjacent to the pixel electrode.
申请公布号 US9235091(B2) 申请公布日期 2016.01.12
申请号 US201414200035 申请日期 2014.03.07
申请人 PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD. 发明人 Ono Kikuo
分类号 G02F1/1362 主分类号 G02F1/1362
代理机构 Hubbs, Enatsky & Inoue PLLC 代理人 Hubbs, Enatsky & Inoue PLLC
主权项 1. A liquid crystal display device, comprising: a first substrate on a display surface side and a second substrate on a rear surface side, the first substrate and the second substrate being placed so as to be opposed to each other with liquid crystal interposed therebetween, the second substrate comprising: a plurality of gate signal lines formed thereon, each of which extends in a row direction;a plurality of data signal lines formed thereon, each of which extends in a column direction;a plurality of pixel electrodes formed thereon, which are provided correspondingly to a plurality of pixels arranged in the row direction and the column direction; anda common electrode formed thereon, which is provided on the display surface side so as to be opposed to the plurality of pixel electrodes, wherein an interline pitch of the plurality of gate signal lines is smaller than an interline pitch of the plurality of data signal lines, wherein, in each of the plurality of pixels, the pixel electrode in a first pixel overlaps and extends to across, in plan view, both a gate signal line for driving the first pixel and a gate signal line of the plurality of gate signal lines which is scanned next to the gate signal line for driving the first pixel, wherein, in the each of the plurality of pixels, in plan view, a first overlapping area of the pixel electrode in a first pixel and the gate signal line for driving the first pixel is smaller than a second overlapping area of the pixel electrode in the first pixel and the gate signal line being scanned next to the gate signal line for driving the first pixel, and wherein the first overlapping area and the second overlapping area are arranged in zigzag.
地址 Hyogo JP