Electronic control unit having integrated circuit element and standalone test unit for integrated circuit element

摘要

There is provided a low-cost electronic control unit that is capable of performing its hardware check every start and stop of the electronic control unit. A monitoring and control circuit section that is an integrated circuit element built in the electronic control unit includes a self-test circuit configured with a built-in self-test control block, scan chain circuits and mask circuitry, and performs a self-test using the built-in self-test control block and a partial combination of the scan chain circuits at start of the operation. In the shipment inspection of the integrated circuit element alone, an external test is performed by a checker microprocessor using an entire combination of the scan chain circuits. Thus, the electronic control unit of low-cost configuration is capable of performing a scan test by making use of part of the scan chain circuits designed for the component inspection.

主权项

1. An electronic control unit having an integrated circuit element, comprising:
an input interface circuit connected to input sensors; an output interface circuit connected to electrical loads; and an integrated circuit element connected with the input interface circuit and the output interface circuit, the integrated circuit element including
a self-test circuit for performing a self-test on the integrated circuit element itself; anda selection command input terminal for selecting a scan mode,the self-test circuit configured with
a built-in self-test control block for generating test pattern for the self-test;scan chain circuits each made up of a plurality of flip-flop circuits internally or additionally provided to be connected with a plurality of circuit components in the integrated circuit element and serially combined with each other; andmask circuitry arranged to connect between input circuit portions and output circuit portions of the plurality of circuit components, for disabling their input and output operations, wherein the selection command input terminal receives a selection command signal selecting any one of a first combination of the scan chain circuits that excludes a scan chain circuit for the built-in self-test control block and a scan chain circuit outside the self-test, and a second combination of the scan chain circuits that includes all scan chain circuits,the built-in self-test control block further including
a scan-pulse output circuit for feeding a first diagnostic pulse-train signal to the front stage of the first combination of scan chain circuits;an expected-value comparison circuit for receiving a first measurement pulse-train signal response to the first diagnostic pulse-train signal and output from the last stage of the first combination of scan chain circuits, and for determining whether or not the received first measurement pulse-train signal agrees with correct pulse-train information corresponding to the first diagnostic pulse-train signal; anda comparison result storing memory for storing normality or non-normality of the determination result, wherein the built-in self-test control block generates an internal-scan enabling signal for enabling the first diagnostic pulse-train signal,the self-test circuit further including:
a pulse input terminal for receiving a second diagnostic pulse-train signal to be input to the front stage of the second combination of scan chain circuits;a pulse output terminal for sending out a second measurement pulse-train signal response to the second diagnostic pulse-train signal; anda control input terminal for receiving an external-scan enabling signal enabling the second diagnostic pulse-train signal, wherein the built-in self-test control block is enabled during a predetermined boot wait period between closure of a power switch feeding power to the integrated circuit element and start of control operation of the integrated circuit element or during a predetermined prolonged power-feed period after closure of the power switch and halt of control operation of the integrated circuit element, and executes the self-test using the first combination of scan chain circuits, andwherein during the execution of the self-test, acquisition of some signals input from the input interface circuit and generation of some signals output to the output interface circuit are disabled by the mask circuitry, and execution of an external test for the second combination of scan chain circuits using the self-test circuit and sending out of the second diagnostic pulse-train signal are performed in a shipment inspection process for the integrated circuit element alone.