| 发明名称 | Method and an apparatus for automatic processor design and verification | ||
| 摘要 | A method and a system embodying the method for automatic application-specific instruction-set processor design and verification, comprising generating programming and simulation tools in accordance with application-specific instruction-set processor specifications automatically by an Electronic Design Automation tool; generating a reference model and a hardware description of the application-specific instruction-set processor in accordance with the application-specific instruction-set processor specifications automatically by the Electronic Design Automation tool; and verifying the hardware description against the reference model is disclosed. | ||
| 申请公布号 | US9235669(B2) | 申请公布日期 | 2016.01.12 |
| 申请号 | US201414183482 | 申请日期 | 2014.02.18 |
| 申请人 | CODASIP S.R.O. | 发明人 | P{hacek over (r)}ikryl Zden{hacek over (e)}k;Husár Adam;Masa{hacek over (r)}ík Karel;Hru{hacek over (s)}ka Tomá{hacek over (s)} |
| 分类号 | G06F17/50 | 主分类号 | G06F17/50 |
| 代理机构 | pkalousek.ip | 代理人 | pkalousek.ip |
| 主权项 | 1. A method for automatic design and verification of an application-specific instruction-set processor, comprising: designing an instruction accurate model in accordance with the application-specific instruction-set processor specifications; designing a cycle accurate model in accordance with the application-specific instruction set processor specifications; generating programming and simulation tools from at least one of the instruction accurate model and the cycle accurate model automatically by the Electronic Design Automation tool; and generating a reference model and a hardware description of the application-specific instruction-set processor in accordance with the application-specific instruction-set processor specifications automatically by the Electronic Design Automation tool; and verifying the hardware description against the reference model. | ||
| 地址 | Brno CZ | ||