Multiple, per sensor configurable FIFOs in a single static random access memory (SRAM) structure

摘要

A device includes one or more sensors, one or more processors, one or more sensors, and a memory. The memory has a first portion, a second portion, and a third portion. The first portion is allocated to storing instructions for execution by the one or more processors. The second portion is allocated to storing data generated by the one or more processor, and the third portion is allocated to storing data from the one or more sensors. The third portion being a first-in-first-out (FIFO) having one or more FIFO portions, The device further includes a control logic operable to allocate the first, second and third portions of the memory, wherein each of one or more FIFO portions is allocated to each of the one or more sensors. The size each of the FIFO portions depends on the bandwidth of the sensors and the number of sensors.

主权项

1. A device comprising:
one or more sensors, each having a bandwidth associated therewith; one or more processors; a memory coupled to the one or more sensors and the one or more processors and having a first portion, a second portion, and a third portion, the first, second, and third portions being contiguous, the third portion being a first-in-first-out (FIFO) having one or more FIFO portions, the first portion allocated to store instructions for execution by a processor of the one or more processors, the second portion allocated to store data generated by the processor, and the third portion allocated to store data from the one or more sensors wherein the sizes of the first, second and third portions of the memory are based on the bandwidth of the one or more sensors; and control logic coupled to the memory and operable to dynamically allocate the first, second and third portions of the memory, wherein each of one or more FIFO portions is allocated to each of the one or more sensors.