| 发明名称 | Method and an apparatus for automatic generation of verification environment for processor design and verification | ||
| 摘要 | A method and a system embodying the method for automatic generation of a verification environment, comprising providing a first model of an application-specific instruction-set processor; providing a second model of the application-specific instruction-set processor; and generating automatically the verification environment from the first model and the second model is disclosed. | ||
| 申请公布号 | US9235670(B2) | 申请公布日期 | 2016.01.12 |
| 申请号 | US201414183498 | 申请日期 | 2014.02.18 |
| 申请人 | CODASIP, s.r.o. | 发明人 | P{hacek over (r)}ikryl Zden{hacek over (e)}k;{hacek over (S)}imková Marcela;Masa{hacek over (r)}ík Karel |
| 分类号 | G06F9/455;G06F17/50 | 主分类号 | G06F9/455 |
| 代理机构 | pkalousek.ip | 代理人 | pkalousek.ip |
| 主权项 | 1. A method for automatic generation of a verification environment, comprising: providing a first model of an application-specific instruction-set processor; providing a second model of the application-specific instruction-set processor; and generating automatically the verification environment from the first model and the second model. | ||
| 地址 | Brno CZ | ||