发明名称 WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE
摘要 A wiring substrate includes a core layer, a first wiring layer, a first insulating layer, a first via wiring, a second wiring layer, a second insulating layer, a second via wiring, a third wiring layer, a third insulating layer, a third via wiring, and a through-wiring. The through-wiring includes upper and lower end surfaces. The upper end surface has an area that is smaller than an area of the lower end surface. The upper surface of the first insulating layer is more flat than the lower surface of the third insulating layer. The second wiring layer has a wiring density that is higher than a wiring density of the first wiring layer.
申请公布号 US2016007460(A1) 申请公布日期 2016.01.07
申请号 US201514790131 申请日期 2015.07.02
申请人 SHINKO ELECTRIC INDUSTRIES CO., LTD. 发明人 SHIMIZU Noriyoshi;GOZU Yusuke;ROKUGAWA Akio
分类号 H05K1/11;H05K1/03;H05K1/18;H05K1/02 主分类号 H05K1/11
代理机构 代理人
主权项 1. A wiring substrate comprising: a core layer having a first surface and a second surface; a first wiring layer formed on the first surface of the core layer; a first insulating layer being formed on a side of the first surface of the core layer to cover the first wiring layer and including an upper surface; a first via wiring being embedded in the first insulating layer and having a first end surface that is exposed from the upper surface of the first insulating layer; a second wiring layer being formed on the upper surface of the first insulating layer and the first end surface of the first via wiring and being directly bonded to the first end surface of the first via wiring; a second insulating layer being formed on the upper surface of the first insulating layer to cover the second wiring layer; a second via wiring being embedded in the second insulating layer and being electrically connected to the second wiring layer; a third wiring layer formed on the second surface of the core layer; a third insulating layer being formed on a side of the second surface of the core layer and including a lower surface; a third via wiring being embedded in the third insulating layer and being electrically connected to the third wiring layer; and a through-wiring that penetrates the core layer from the first surface to the second surface and electrically connects the first wiring layer and the third wiring layer; wherein the through-wiring includes upper and lower end surfaces, wherein the upper end surface has an area that is smaller than an area of the lower end surface, wherein the upper surface of the first insulating layer is more flat than the lower surface of the third insulating layer, and wherein the second wiring layer has a wiring density that is higher than a wiring density of the first wiring layer.
地址 Nagano JP