发明名称 MICROCONTROLLER WITH MULTIPLE POWER MODES
摘要 A microcontroller operable in a high power mode and a low power unit (LPU) run mode includes primary and LPU domains, primary and LPU mode controllers, and primary and LPU clock generator modules. The primary domain includes a first set of circuits and a first set of cores. The LPU domain includes second and third sets of circuits, a second set of cores, and a switching module. In the high power mode, the switching module connects the first and second sets of cores to at least one of the first, second and third sets of circuits, while in the LPU run mode, the switching module isolates the LPU domain from the primary domain and activates a small microcontroller system (SMS) that includes the LPU domain, the LPU mode controller and the LPU clock generator module. The SMS has further low power modes within the LPU run mode.
申请公布号 US2016004292(A1) 申请公布日期 2016.01.07
申请号 US201414321838 申请日期 2014.07.02
申请人 Sharda Garima;Culshaw Carl;Devine Alan;Pathak Akshay K.;Robertson Alistair P. 发明人 Sharda Garima;Culshaw Carl;Devine Alan;Pathak Akshay K.;Robertson Alistair P.
分类号 G06F1/32;G06F13/40 主分类号 G06F1/32
代理机构 代理人
主权项 1. An integrated circuit (IC) operable in a high power mode and a low power unit (LPU) run mode, comprising: a primary domain including: a first set of circuits;a first set of cores having at least one core that operates when the IC is in the high power mode and is powered off when the IC is in the LPU run mode; anda first cross-bar bus, connected between the first set of cores and the first set of circuits, that configures a connection between the first set of cores and the first set of circuits; and a LPU domain including: second and third sets of circuits;a second set of cores having at least one core that operates when the integrated circuit is in the high power and LPU run modes; anda switching module, connected to the second set of cores, the first cross-bar bus, and the second and third sets of circuits, that connects the second set of cores to at least one of the first, second and third sets of circuits by way of the first cross-bar bus when the IC is in the high power mode, and connects the second set of cores directly to at least one of the second and third sets of circuits when the IC is in the LPU run mode.
地址 Ghaziabad IN