SEMICONDUCTOR MEMORY APPARATUS

摘要

A semiconductor memory apparatus may include a refresh mode control circuit configured to enable a row address increase signal when all banks capable of being designated by a bank address in a refresh operation are all designated. The semiconductor memory apparatus may also include and a row address generation circuit configured to increase a value of a row address when the row address increase signal is enabled.

主权项

1. A semiconductor memory apparatus comprising:
a refresh mode selection circuit configured to generate a first refresh mode signal and a second refresh mode signal in response to an external command and a refresh control signal; a first refresh mode control circuit configured to generate a first row address increase signal in response to a bank address and the first refresh mode signal; a second refresh mode control circuit configured to generate a second row address increase signal in response to the second refresh mode signal; and a row address generation circuit configured to generate a row address in response to the first and second row address increase signals, wherein the first refresh mode control circuit enables the first row address increase signal after all preset banks to be designated by the bank addresses are activated, when the first refresh mode signal is enabled.