Semi-Analog FIR Filter With High Impedance State

摘要

A system and method is disclosed for placing some of the elements of a FIR filter into a high impedance state in certain situations. When it is detected that the signal to an impedance element is the same as the previous value, then the driver of that impedance element is “turned off” or goes into a high impedance state, so that no current flows through that impedance element, and it no longer contributes to the filter output. Alternatively, if the impedance elements are the same between two adjacent taps of the delay line, the driver of one of those impedance elements may be turned off or go into a high impedance state. The technique may be particularly useful in differential output filters. Turning off a driver effectively removes the attached impedance element from the filter and reduces current flow and power consumption, thus extending battery life in mobile devices.

主权项

1. A finite impulse response filter comprising:
an input configured to receive an input signal; a delay line comprising a plurality of delay elements in series and connected to the input for propagating and delaying the input signal; a plurality of buffers, each buffer in the plurality of buffers coupled to the delay line after a separate one of the plurality of delay elements so as to receive the delayed input signal after the input signal has passed through the connected delay element; a plurality of control elements, each control element in the plurality of control elements coupled to a separate one of the plurality of buffers and configured to detect the delayed input signal immediately before and after the delay element to which the buffer is coupled and cause the buffer connected to the control element to not pass the delayed input signal through the buffer if the delayed input signal immediately before the delay element to which the buffer is coupled is the same as the delayed input signal after the same delay element; a plurality of impedance elements having impedance values, each of the plurality of impedance elements coupled to a different one of the plurality of buffers than each other impedance element in the plurality of impedance elements so as to receive a delayed input signal when the connected buffer passes the delayed input signal and provide an output weighted by the impedance value of the impedance element, the impedance values of the plurality of impedance elements selected such that the sum of the outputs of the plurality of impedance elements produces a selected frequency response to the input signal; and an output coupled to the plurality of impedance elements to produce an output signal.