发明名称 |
Semiconductor Device And Manufacturing Method Thereof |
摘要 |
An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided. |
申请公布号 |
US2016005875(A1) |
申请公布日期 |
2016.01.07 |
申请号 |
US201514848492 |
申请日期 |
2015.09.09 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
YAMAZAKI Shunpei;HOSOBA Miyuki;Sakata Junichiro;Kuwabara Hideaki |
分类号 |
H01L29/786;H01L29/45;H01L29/51;H01L27/12 |
主分类号 |
H01L29/786 |
代理机构 |
|
代理人 |
|
主权项 |
1. (canceled) |
地址 |
Atsugi-shi JP |