MULTIPLE-BIT-PER-CELL, INDEPENDENT DOUBLE GATE, VERTICAL CHANNEL MEMORY HAVING SPLIT CHANNEL

摘要

A vertical channel 3D NAND array is configured for independent double gate operation, establishing two memory sites per frustum of a vertical channel column, and in addition, for multiple-bit-per-cell operation. The memory device can comprise even and odd stacks of conductive strips. Active pillars are arranged between corresponding even and odd stacks of conductive strips. A 3D array includes even memory cells accessible via the active pillars and conductive strips in the even stacks and odd memory cells accessible via the active pillars and conductive strips in the odd stacks of conductive strips. Control circuitry is configured to apply different bias voltages to the even and odd conductive strips, and execute a program operation by which more than one bit of data is stored in both the even memory cell and odd memory cell in a given frustum of a selected active strip.

主权项

1. A memory device, comprising:
a plurality of stacks of conductive strips, the plurality of stacks including even stacks and odd stacks having sidewalls, at least some of the conductive strips in the stacks configured as word lines; data storage structures on the sidewalls of the even and odd stacks; and a plurality of vertical channel structures between corresponding even and odd stacks of conductive strips in the plurality of stacks, vertical channel structures in the plurality comprising even and odd semiconductor films having outside surfaces and inside surfaces, the outside surfaces disposed on the data storage structures on the sidewalls of the corresponding even and odd stacks in the plurality of stacks forming a 3D array of memory cells, the inside surfaces being separated.