| 发明名称 |
NON-ATOMIC SPLIT-PATH FUSED MULTIPLY-ACCUMULATE |
| 摘要 |
A microprocessor performs a fused multiply-accumulate operation of a form ±A*B±C using first and second execution units. An input operand analyzer circuit determines whether values of A, B and/or C meet a sufficient condition to perform a joint accumulation of C with partial products of A and B. The first instruction execution unit multiplies A and B and jointly accumulates C to partial products of A and B when the values of A, B and/or C meet a sufficient condition to perform a joint accumulation of C with the partial products of A and B. The second instruction execution unit separately accumulates C to the products of A and B when the values of A, B and/or C do not meet a sufficient condition to perform a joint accumulation of C with the partial products of A and B. |
| 申请公布号 |
US2016004504(A1) |
申请公布日期 |
2016.01.07 |
| 申请号 |
US201514748817 |
申请日期 |
2015.06.24 |
| 申请人 |
VIA ALLIANCE SEMICONDUCTOR CO, LTD. |
发明人 |
ELMER Thomas |
| 分类号 |
G06F7/483;G06F9/30;G06F7/544 |
主分类号 |
G06F7/483 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A microprocessor operable to perform a fused multiply-accumulate operation of a form ±A*B±C, wherein A, B, and C are input operands, the microprocessor comprising:
an input operand analyzer circuit that determines whether values of A, B and/or C meet a sufficient condition to perform a joint accumulation of C with partial products of A and B; a first instruction execution unit that multiplies A and B and jointly accumulates C to partial products of A and B when the values of A, B and/or C meet a sufficient condition to perform a joint accumulation of C with the partial products of A and B; and a second instruction execution unit that separately accumulates C to the products of A and B when the values of A, B and/or C do not meet a sufficient condition to perform a joint accumulation of C with the partial products of A and B. |
| 地址 |
Shanghai CN |
