Edge Generator-Based Phase Locked Loop Reference Clock Generator for Automated Test System

摘要

An automatic test system configured for generating a periodic signal of a programmable frequency. The automatic test system may comprise a clock, an edge generator coupled to the clock, a phase locked loop, and a delay adjustment circuit. The edge generator may comprise an edge generator output, an enable input and a delay input. The edge generator may produce at the edge generator output a signal with a delay relative to an edge of the clock specified by a value at the delay input in each cycle of the clock for which the enable input is asserted. The phase locked loop may comprise a reference input and a phase locked loop output configured to provide the periodic signal of the programmable frequency. The delay adjustment circuit may comprise an accumulator that may increase in value by a programmed amount for each cycle of the clock.

主权项

1. A periodic signal generation circuit for generating a periodic signal of a programmable frequency, the periodic signal generation circuit comprising:
a phase locked loop, the phase locked loop comprising:
a controllable oscillator comprising a controllable oscillator output and a control input, the controllable oscillator being configured to produce the periodic signal at the controllable oscillator output with a frequency controlled by a control signal at the control input; anda comparator comprising a first input and a second input and a comparator output, the comparator being configured to produce a signal at the comparator output, wherein the signal is representative of a difference in a phase characteristic between a first signal at the first input and a second signal at the second input, wherein the comparator output is coupled to the control input of the controllable oscillator, and wherein the controllable oscillator output is coupled to the second comparator input; a programmable delay pulse generator circuit comprising a delay control input and an output, the output of the programmable delay pulse generator circuit being coupled to the first input of the comparator, the programmable delay pulse generator circuit being configured to output a pulse at the output of the programmable delay pulse generator circuit with a programmable delay following a transition of a reference signal; and an adjustment circuit to compute a value of the programmable delay for each of a plurality of cycles of the first signal.