发明名称 FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME
摘要 A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
申请公布号 US2016005484(A1) 申请公布日期 2016.01.07
申请号 US201514856261 申请日期 2015.09.16
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Lee Kyeong-Han;Kwon Seok-Cheon;Lee Dong-Yang
分类号 G11C16/26;G11C16/32;G11C16/08 主分类号 G11C16/26
代理机构 代理人
主权项 1. A nonvolatile memory device comprising: a nonvolatile memory cell array; an x-selector configured to select a plurality of memory cells among the nonvolatile memory cell array based on an address; and a page buffer configured to read user data from the plurality of memory cells, a peripheral circuit configured to receive a command, to select one of an SDR mode and a DDR mode in response to the command, and to receive a first signal toggling between a high level and a low level; wherein, in the SDR mode, when data is output in synchronization with the first signal, the data is maintained with the same value at a rising edge and a falling edge of each of a plurality of periods of the first signal during a data output cycle, in the DDR mode, the data is output in synchronization with both the rising edge and the falling edge of the first signal during the data output cycle, the peripheral circuit is configured to output identification data only in the SDR mode, the peripheral circuit is configured to output the user data in both the SDR mode and the DDR mode, and the identification data includes at least one of a maker code, a device code, a page size and a block size of the nonvolatile memory device.
地址 Suwon-si KR