| 摘要 |
A PLL circuit that operates in synchronization with an operating clock and generates and outputs a generated clock in synchronization with an external clock, including a multi-phase clock generating unit that generates multi-phase clocks including n clocks which have a same frequency and differ in phase one another, one of the clocks in the multi-phase clock being the operating clock, a frequency signal generating unit that outputs a frequency signal based on a phase difference signal from a phase comparator, an oscillating unit that generates and outputs a clock oscillating with a frequency corresponding to the frequency signal, and the phase comparator that measures a time difference between rising times or falling times of the inputted external clock and the oscillating unit based on the n clocks in the multi-phase clocks, and outputs a phase difference signal indicating the time difference based on a result of the measurement. |
