发明名称 半導体集積回路装置
摘要 Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
申请公布号 JP5840092(B2) 申请公布日期 2016.01.06
申请号 JP20120186906 申请日期 2012.08.27
申请人 ルネサスエレクトロニクス株式会社 发明人 長田 健一;南 正隆;池田 修二;石橋 孝一郎
分类号 H01L21/8244;H01L27/10;H01L27/11 主分类号 H01L21/8244
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