发明名称 Nonvolatile semiconductor memory device
摘要 A control circuit provides an at least partially negative threshold voltage distribution to a memory cell, thereby erasing retained data of the memory cell, and provides multiple levels of positive threshold voltage distributions thereto, thereby programming multiple levels of data to the memory cell. The control circuit, when executing a program operation to the memory cell, executes a first program operation that provides the multiple levels of positive threshold voltage distributions to a first memory cell which is a memory cell subject to program, and executes a second program operation that provides a positive threshold voltage distribution, to a second memory cell adjacent to the first memory cell, irrespective of (regardless of) whether data to be programmed to the second memory cell is (already) present in the second memory cell or not.
申请公布号 US9230665(B2) 申请公布日期 2016.01.05
申请号 US201113816799 申请日期 2011.09.22
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 Hosono Koji
分类号 H01L27/115;H01L21/8234;H01L27/06;G11C16/12;G11C11/56;G11C16/04;G11C16/10;G11C16/34 主分类号 H01L27/115
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A nonvolatile semiconductor memory device, comprising: a memory cell array including a first memory cell and a second memory cell; and a control circuit configured to execute a write operation for the first memory cell when receiving a write command and an address corresponding to the first memory cell, the write operation including a first operation and a second operation, the control circuit being configured to execute the first operation in the condition that a program voltage is applied to a gate of the first memory cell and execute the second operation so that a threshold voltage of the second memory cell is changed from a negative value to a positive value without receiving data from outside of the nonvolatile semiconductor memory, wherein the control circuit is configured to execute the second operation after the first operation, one of the memory cells is capable of retaining 2-or-more-bits data, and the control circuit is configured to, when the control circuit receives a certain part of the 2-or-more-bits data as first data, start the first operation for programming part of the first data and then start the second operation, and when the control circuit receives complete 2-or-more-bits data after the first operation for programming the part of the first data and before the second operation, execute the first operation for programming complete 2-or-more-bits data as the first data prior to the second operation.
地址 Tokyo JP
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