Refresh scheme for memory cells with next bit table

摘要

A memory refresh control technique allows flexible internal refresh rates based on an external 1× refresh rate and allows skipping a refresh cycle for strong memory rows based on the external 1× refresh rate. A memory controller performs a memory refresh by reading a refresh address from a refresh address counter, reading a weak address from a weak address table and generating a next weak address value based at least in part on a next bit sequence combined with the weak address. The memory controller compares the refresh address to the weak address and to the next weak address value. Based on the comparison, the memory controller selects between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address.

主权项

1. A memory refresh method within a memory controller, comprising:
reading a refresh address from a refresh address counter; reading a weak address from a weak address table; generating a next weak address value based at least in part on a next bit sequence combined with the weak address; comparing the refresh address to the weak address and to the next weak address value; and selecting between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address based at least in part on the comparing.