Resonant clock amplifier with a digitally tunable delay

摘要

A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.

主权项

1. A device comprising:
a clock circuit comprising amplifiers, at least one of the amplifiers being a resonant amplifier, the clock circuit being configured to produce amplified clock signals derived from a source clock signal, wherein the amplified clock signals comprise at least one amplified and programmably delayed clock signal; a first circuit configured to latch an input data stream using a first amplified clock signal produced by the clock circuit, the first amplified clock signal having a first frequency; and a second circuit that is electrically coupled to the first circuit, the second circuit configured to demultiplex the data stream latched by the first circuit using at least a second amplified clock signal produced by the clock circuit, the second amplified clock signal having a second frequency that is less than the first frequency.