| 发明名称 | Analog circuits having improved transistors, and methods therefor | ||
| 摘要 | Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. | ||
| 申请公布号 | US9231541(B2) | 申请公布日期 | 2016.01.05 |
| 申请号 | US201414500236 | 申请日期 | 2014.09.29 |
| 申请人 | Mie Fujitsu Semiconductor Limited | 发明人 | Clark Lawerence T.;Thompson Scott E. |
| 分类号 | H03F3/45 | 主分类号 | H03F3/45 |
| 代理机构 | Baker Botts L.L.P. | 代理人 | Baker Botts L.L.P. |
| 主权项 | 1. A circuit, comprising: a plurality of transistors having controllable current paths coupled between at least a first node and a second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors operates with an applied body bias, and has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a doped screen layer formed over a doped body region, with the doped screen layer extending between and in contact with a source and a drain. | ||
| 地址 | Kuwana, Mie JP | ||