发明名称 CLOCK RECOVERY SCHEME AT DISPLAYPORT RECEIVER
摘要 A receiver according to the present invention comprises: an all digital clock and data recovery (ADCDR) (10) provided with a digitally controlled oscillator (DCO) for performing a function of recovering parallel data and a link symbol clock from serial data streams; a code storage unit (20) for storing a DCO code determining an output frequency of the DCO when link training succeeds, as a receiver used in digital display interface including at least video data transfer; and an error detector (30) for detecting an link error using the parallel data and the link symbol clock recovered, wherein the clock is recovered by applying the DCO code stored in the code storage unit (20) to the DCO of the ADCDR (10) if the error detector (30) detects an link error. According to the present invention, if the link error is detected during video data transfer, the clock is immediately recovered by applying the DCO code stored to the DCO of the ADCDR, thereby allowing data transfer to be normalized in a remarkably short amount of time, and thus exposure time of an abnormal screen or noise can be significantly reduced.
申请公布号 KR101582168(B1) 申请公布日期 2016.01.05
申请号 KR20140161699 申请日期 2014.11.19
申请人 SNU R&DB FOUNDATION 发明人 KIM, TAE HO;JEONG, DEOG KYOON
分类号 H04N21/242;H04N21/40 主分类号 H04N21/242
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