Low power oversampling with reduced-architecture delay locked loop

摘要

In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.

主权项

1. A mobile system comprising:
a radio frequency (RF) transceiver to communicate wirelessly via an antenna; a baseband processor coupled to the RF transceiver, the baseband processor including at least one core and a receiver logic, the receiver logic comprising:
a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal;a controller unit to generate a delay signal based on the phase difference; anda set of voltage-controlled delay buffers to generate a plurality of phase outputs based on the delay signal, the plurality of phase outputs provided to a clock generator unit to generate an oversampled clock signal for data recovery; and a touchscreen display coupled to the baseband processor.