| 发明名称 | Electronic chip with means of protecting its back face | ||
| 摘要 | An electronic chip is provided, including an electronic circuit located at a front face of a substrate; a capacitive element placed at a back face of the substrate and facing the electronic circuit, and electrically connected to the electronic circuit by a first electrical connection and a second electrical connection, the first electrical connection including at least a first electrically conducting via passing through the substrate, the electronic circuit being configured to measure a value of electrical capacitance of the capacitive element between the first and the second electrical connections; and a plurality of second vias or trenches passing through the back face of the substrate and a part of the thickness of the substrate, and extending toward the electronic circuit such that bottom walls of the plurality of second vias or trenches are separated from the electronic circuit by at least one non-zero distance. | ||
| 申请公布号 | US9230923(B2) | 申请公布日期 | 2016.01.05 |
| 申请号 | US201414510525 | 申请日期 | 2014.10.09 |
| 申请人 | Commissariat à l'énergie atomique et aux énergies alternatives | 发明人 | Lamy Yann;Merle Alain;Parat Guy-Michel;Tria Assia |
| 分类号 | H01L23/00;H01L49/02;H01L21/768;G06F21/86;H01L29/66;H01L29/94;H01L27/02;H01L27/06;H01L23/522 | 主分类号 | H01L23/00 |
| 代理机构 | Oblon, McClelland, Maier & Neustadt, L.L.P. | 代理人 | Oblon, McClelland, Maier & Neustadt, L.L.P. |
| 主权项 | 1. An electronic chip, comprising: an electronic circuit located at a front face of a substrate; at least one capacitive element placed at least at a back face of the substrate and at least partly facing the electronic circuit, and electrically connected to the electronic circuit by at least one first electrical connection and one second electrical connection, the at least one first electrical connection including at least one first electrically conducting via passing through the substrate,the electronic circuit being configured to measure a value of electrical capacitance of the at least one capacitive element between the at least one first electrical connection and the second electrical connection; and a plurality of second vias or trenches passing through the back face of the substrate and a part of the thickness of the substrate, and extending toward the electronic circuit such that bottom walls of the plurality of second vias or trenches are separated from the electronic circuit by at least one non-zero distance, wherein each bottom wall of each via or trench of said plurality is disposed opposite to a lower surface of the electronic circuit, and is arranged in the substrate substantially within a region defined by a lateral width of the electronic circuit. | ||
| 地址 | Paris FR | ||