Metal line connection for improved RRAM reliability, semiconductor arrangement comprising the same, and manufacture thereof

摘要

An integrated circuit device includes an array of RRAM cells, an array of bit lines for the array of RRAM cells, and an array of source lines for the array of RRAM cells. Both the source lines and the bit lines are in metal interconnect layers above the RRAM cells. The source line are thereby provided with a higher than conventional wire size, which increases the reset speed by approximately one order of magnitude. The lifetime of the RRAM transistors and the durability of the RRAM device are consequentially improved to a similar degree.

主权项

1. An integrated circuit device, comprising:
an array of RRAM cells; an array of bit lines connected to the RRAM cells of the array, each of the bit lines having a first cross-sectional area; and an array of source lines for the RRAM cells of the array, each of the source lines having a second cross-sectional area; wherein the second cross-sectional area is greater than the first cross-sectional area; and the source lines and bit lines are configured to carry current for setting and resetting the RRAM cells.