Semicondutor apparatus for controlling back bias

摘要

A semiconductor apparatus includes a back bias control block, a first back bias switching block and second back bias switching block. The back bias control block is configured to generate a first P channel control signal and a second N channel control signal. The first back bias switching block is configured to provide one of first and second high voltages as a first P channel back bias of a first circuit in response to the first P channel control signal, and to provide one of first and second low voltages as a first N channel back bias of the first circuit in response to the first N channel control signal. The second back bias switching block is configured to provide one of the first and second high voltages as a second P channel back bias of a second circuit in response to the second P channel control signal, and to provide one of the first and second low voltages as a second N channel back bias of the second circuit in response to the second N channel control signal.

主权项

1. A semiconductor apparatus comprising:
a back bias control block configured to generate a first P channel control signal, a second P channel control signal, a first N channel control signal and a second N channel control signal according to an operation mode based on a command signal; a first back bias switching block configured to provide one of a first high voltage and a second high voltage as a first P channel back bias of a first internal circuit in response to the first P channel control signal, and to provide one of a first low voltage and a second low voltage as a first N channel back bias of the first internal circuit in response to the first N channel control signal; and a second back bias switching block configured to provide one of the first high voltage and the second high voltage as a second P channel back bias of a second internal circuit in response to the second P channel control signal, and to provide one of the first low voltage and the second low voltage as a second N channel back bias of the second internal circuit in response to the second N channel control signal, wherein the first P channel control signal includes a first high voltage control signal and a second high voltage control signal, and wherein the back bias control block is configured to generate the first high voltage control signal having the first low voltage and the second high voltage control signal having the second high voltage in a first operation mode, and to generate the first high voltage control signal having the first high voltage and the second high voltage control signal having the first low voltage in a second operation mode and in a third operation mode.