发明名称 |
Multi-core integrated circuit configurable to provide multiple logical domains |
摘要 |
Apparatuses, methods and storage media associated with integrated circuits (IC) or system-on-chips (SOC) are disclosed herein. In embodiments, a multi-core IC may include a number of central processing units (CPUs), and a number of input/output (I/O) resources. The IC may further include a switch fabric configured to couple the CPUs with the I/O resources, and a register to be selectively configured to exclusively couple one of the CPUs with one of the I/O resources to form a logical domain that computationally isolates the one CPU and the one I/O resource from other CPUs and other I/O. Other embodiments may be described and claimed. |
申请公布号 |
US9229895(B2) |
申请公布日期 |
2016.01.05 |
申请号 |
US201213615442 |
申请日期 |
2012.09.13 |
申请人 |
Intel Corporation |
发明人 |
Coleman James A.;Srivastava Durgesh;Rogers Gerald;Oehrlein Scott M. |
分类号 |
G06F13/40 |
主分类号 |
G06F13/40 |
代理机构 |
Schwabe, Williamson & Wyatt, P.C. |
代理人 |
Schwabe, Williamson & Wyatt, P.C. |
主权项 |
1. A multi-core integrated circuit (IC) comprising:
a computer processing unit (CPU) in a first logical division of the multi-core IC; an input/output (I/O) resource in a second logical division of the multi-core IC; a register coupled with a switch fabric to cooperate with the switch fabric for the switch fabric to:
exclusively couple the CPU with the I/O resource to form a logical domain that computationally isolates the CPU and the I/O resource from other CPUs and other I/O resources of the multi-core IC;provide a first logical channel in the first logical division to couple the CPU with a memory resource in the first logical division in the logical domain; andprovide a second logical channel in the second logical division to couple the I/O resource with the first logical division in the logical domain. |
地址 |
Santa Clara CA US |