发明名称 Memory device
摘要 A memory device includes a memory cell storing data as stored data, an output signal line, and a wiring to which a voltage is applied. The memory cell includes a comparison circuit performing a comparison operation between the stored data and search data and taking a conduction state or a non-conduction state in accordance with the operation result, and a field-effect transistor controlling writing and holding of the stored data. A voltage of the output signal line is equal to the voltage of the wiring when the comparison circuit is in the conduction state.
申请公布号 US9230648(B2) 申请公布日期 2016.01.05
申请号 US201213443959 申请日期 2012.04.11
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Matsubayashi Daisuke
分类号 G11C15/00;G11C15/04 主分类号 G11C15/00
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A semiconductor device comprising: a memory cell comprising: a first transistor;a second transistor;a third transistor;a fourth transistor; anda fifth transistor, wherein a gate of the first transistor is electrically connected to a word line, wherein one of a source and a drain of the first transistor is electrically connected to a data line, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, wherein one of a source and a drain of the second transistor is electrically connected to an output signal line, wherein a gate of the third transistor is electrically connected to the data line, wherein one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the fourth transistor, wherein a gate of the fifth transistor is electrically connected to the data line, wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the third transistor, and wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the fifth transistor.
地址 Atsugi-shi, Kanagawa-ken JP