CLOCK GENERATING CIRCUIT OF REDUCING MODE THE STANDBY POWER AND FLYBACK CONVERTER THEREOF

摘要

The present invention relates to a clock generation circuit including a reducing mode of standby power, capable of easily controlling a slip mode frequency suitable for a kind of an electronic device and maximally extending a gate off section to minimize standby power consumption. The clock generation circuit drives a gate of a transistor in the reducing mode of the standby power by generating a bundle of frequencies according to a preset duty ratio when a slip mode signal is inputted to reduce the standby power from the outside. The clock generation circuit includes: a main clock unit providing a first clock diverged in a preset cycle; an auxiliary clock unit generating and providing a frequency lower than the frequency of the first clock by using the first clock; a step counter performing counting and calculating operations from a preset first bit to a second bit higher than the first bit according to the frequency of the first clock; a latch unit performing a reset when a step counter counts to the second bit since a set input is connected to the output of a first multiplexer and a reset input is connected to the output of the step counter; and an output unit outputting the bundle of the frequencies according to the output of the latch unit and the first clock.